module common_ram_1r1w #(
    parameter ADDR_WIDTH = 8,
    parameter DATA_WIDTH = 4,
    parameter DEPTH      = 1 << ADDR_WIDTH
) (
    input  logic                    clk,
    input  logic                    wr_en,
    input  logic [  ADDR_WIDTH-1:0] wr_addr,
    input  logic [DATA_WIDTH*8-1:0] wr_data,
    input  logic [  DATA_WIDTH-1:0] wr_mask,
    input  logic                    rd_en,
    input  logic [  ADDR_WIDTH-1:0] rd_addr,
    output logic [DATA_WIDTH*8-1:0] rd_data
);
    logic [DATA_WIDTH*8-1:0] ram[0:DEPTH-1];

    always_ff @(posedge clk) begin
        if (wr_en) begin
            for (int i = 0; i < DATA_WIDTH; i++) begin
                if (wr_mask[i]) begin
                    ram[wr_addr][i*8+:8] <= wr_data[i*8+:8];
                end
            end
        end
    end

    always_ff @(posedge clk) begin
        if (rd_en) begin
            rd_data <= ram[rd_addr];
        end
    end

endmodule
